Vlsi Design And Eda Tools By Sarkar And Sarkar

Amandeep Kaur

Assistant Professor

Electrical Engineering

IIT Jodhpur

Biography

I am an Assistant Professor in the department of Electrical Engineering, Indian Institute of Technology Jodhpur. My research is focussed on analog and mixed signal integrated circuit design which is generic as well as application specific like CMOS image sensors and biomedical circuits and systems.

I received my doctoral degree in the department of Electrical Engineering from Indian Institute of Technology Delhi, 2019. During my Ph.D., I have designed and characterized various integrated circuits like comparators, LDO, single stage ADC, two stage ADC, hybrid ADC, and two complete camera systems for high speed and low power applications. The work is published in elite transactions and conferences.

If anyone is interested in the area of analog and mixed signal VLSI design, then feel free to contact me.

Interests

Analog/Mixed Signal IC Design
Data Converters (ADC, DAC)
Interfacing Circuits/Readout Electronics
Biomedical Circuits and Systems
CMOS Image Sensors

Education

PhD in Electrical Engineering, 2019

IIT Delhi
M.Tech in VLSI Design, 2012

Thapar University
B.Tech in ECE, 2010

Kurukshetra University

Teaching

Courses

EEL7060 (July 2019 - Nov 2019): Analog and Interfacing Circuits

EEL7440 (Jan 2020 - ): Image Sensor Design and Applications

CSL7333 (Jan 2020 - ): Neuromorphic Hardware Implementation

Labs

EEP7030 (July 2019 - Nov 2019): Sensors and IoT Lab

EEP7110 (Jan 2020 -): Integrated Circuit Design Lab

Experience

Assistant Professor

Indian Institute of Technology Jodhpur

Sep 2019 – Present Jodhpur

Young Faculty Associate

Indian Institute of Technology Jodhpur

May 2019 – Sep 2019 Jodhpur

Assistant Professor

Sharda University

Jul 2012 – Jul 2013 Greater Noida

People

Ph.D Students

Wilfred Kisku
Bibhudutta Satapathy (M.Tech - PhD dual degree)

M.Tech Students

Anjana Singh
Siddhant Srivastava
Swapnil Bande
Varun Kumar

Research

High frame rate CMOS image sensor: A CMOS image sensor with column-parallel cyclic ADC is designed and fabricated in AMS 350 nm CMOS process. All the associated circuits including pixel array, ADC, vertical scanners, reference generation, clock circuitry etc are integrated on the same integrated circuit. The camera results in a frame rate of 1300 fps. The layout and the raw images captured from the designed camera are shown.

Layout of high frame rate CMOS image sensor

Raw images captured from my own designed high speed camera

A power efficient CMOS image sensor: The CMOS image sensor with column-parallel hybrid ADC is designed and fabricated in AMS 350 nm CMOS process.

Raw images captured from my own designed power efficient camera

A two-stage cyclic ADC: The two-stage cyclic ADC with a 2.5-bit/phase architecture is designed and fabricated in UMC 180 nm CMOS process. The pipelined operation of the two stages along with the relaxed design constraints of the second stage resulted in a competitive performance as compared to the state-of-the-art. The microchip photograph and the measured non linearities are shown.

Microchip photograph of two-stage cyclic ADC

A single stage cyclic ADC: An area efficient and low power single stage cyclic ADC using 2.5-bits in 1.5-bit framework is designed and fabricated in UMC 180 nm CMOS technology. In natural images, the neighbouring pixels contain almost similar information. Instead of reading the entire pixel values, only the difference between the pixels is read. The ADC resolves the delta difference, which reduces the number of clock cycles and hence the readout power. These ADCs are also preferred for biomedical applications.

Microchip photograph of single-stage cyclic ADC

Low latency and low power comparator: An adaptive sampling based low latency and a low power comparator is designed and fabricated in UMC 180 nm CMOS process. Circuit consumes total power of 4.289 microW while operating at the clock frequency of 20 MHz. Measurement results shows the reduction in comparator latency by 75% compared to the state of the art comparators.

Measurement results and Microchip photograph of comparator

Publications

Journal papers

A. Kaur, D. Mishra, Amogh, and M. Sarkar, "On-array compressive acquisition in CMOS image sensors using accumulated spatial gradients", IEEE Transactions on Circuits and Systems for Video Technology, vol. 31, no. 2, pp. 523 - 532, 2021.
A. Kaur, D. Mishra and M. Sarkar, "A 12-bit, 2.5-bit/phase column-parallel cyclic ADC", IEEE Transactions on Very Large Scale Integration Systems, vol. 27, no. 1, pp. 248-52, 2019.
A. Kaur, D. Mishra, and M. Sarkar, "A power efficient image sensor readout with on-chip delta-interpolation using reconfigurable ADC", accepted in IEEE Sensors Journal, 2019
A. Kaur, D. Mishra, S. Jain and M. Sarkar, "Content Driven on-chip Compression and Time Efficient Reconstruction for Image Sensor Applications", IEEE Sensors Journal, vol. 18, no. 22, pp. 9169 - 9179, 2018.

Conference papers

B. Satapathy, A. Kaur, "A Low Kickback Noise and Low Power Dynamic Comparator", accepted in IEEE International Midwest Symposium on Circuits & Systems (MWSCAS), 2021.
V. Kumar, B. Satapathy, W. Kisku, A. Kaur, D. Mishra, "CMOS Image Sensor with Adaptive Readout Scheme for Low Power Applications", accepted in IEEE International Midwest Symposium on Circuits & Systems (MWSCAS), 2021.
W. Kisku, A. Kaur, D. Mishra, "On-Chip Pixel Reconstruction Using Simple CNN for Sparsely Read CMOS Image Sensor", accepted in IEEE International Conference on Artificial Intelligence Circuits & Systems (AICAS), 2021.
B. Satapathy, A. Kaur, "A High speed, Low Energy Comparator Based on Current Recycling Approach", accepted in IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
A. Kaur, Karthik M. B. and M. Sarkar, "A CMOS Image Sensor with column-Parallel cyclic-SAR ADC", accepted in IEEE International Symposium on Circuits and Systems (ISCAS), Spain, 2020.
A. Kaur and D. Mishra, "A reconfigurable cyclic ADC for Biomedical Applications", IEEE Biomedical Circuits and Systems Conference, 2019.
A. Kaur, D. Mishra and M. Sarkar, "A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS image sensors", IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5, 2018.
A. Kaur, D. Mishra and M. Sarkar, "An on-chip interpolation based readout scheme for low-power, high-speed CMOS image sensors", IEEE Sensors conference, pp. 1-5, 2018.
A. Kaur, D. Mishra, and M. Sarkar, "A super-pixel based on-chip image compression for high speed CMOS image sensors", IEEE International Conference on Electron Devices and Solid-State Circuits, pp. 1-2, 2017.
A. Kaur, A. Shrivastava, and M. Sarkar, "A 1.2 V, 33 ppm/oC, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIS", IEEE International SoC Design conference, pp. 111-112, 2017.
A. Kaur and M. Sarkar, "A low power low latency comparator for ramp ADC in CMOS imagers", IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1466-1469, 2016.

Professional Activities

Reviewer of IEEE TCAS - II, IEEE TVLSI, IEEE TCSVT, IEEE Sensors Journal.
Reviewer of IEEE ISCAS conference.

Projects

An endoscopic camera system, BIG GRANT approved by BIRAC *
A programmable CMOS image sensor for high speed, low power and low noise applications, funded by SERB as a startup research grant *
Establishment of AI-Based Platform to Monitor and Identify Smell, Taste and Key COVID19 Therapeutic Hotspots, funded by DST *

Academic Activities

Department Faculty Board (DFB) Convener.
Member Ph.D. Admission Committee.
Member M.Tech Admission Committee.

Awards and Honors

Awards

Best among top 5% papers in IEEE Sensors, 2018.
Best paper award in IEEE ISOCC, 2017.

Honors

Gold medal in B.Tech, 2010.